AMIQ is a company which has pioneered the integrated development environments (IDEs) in hardware design and verification. They have focused on providing software tools that help engineers increase the speed and quality of code development, simplify maintenance, improve testbench reliability, and implement best coding practices.

www.amiq.com
  • DVT Eclipse IDE: Design and Verification Tools (DVT) is the first integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL.
  • Verissimo SystemVerilog Testbench Linter: Verissimo is a static code analysis tool that allows engineers accurately identify SystemVerilog improper language, semantics, and styling usage, as well as verification methodology violations.
  • Specador Documentation Generator: Specador is a tool that automatically generates accurate HTML documentation from source code comments.

Arteris provides Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) to System on Chip (SoC) makers so they can reduce cycle time, increase margins, and easily add functionality. Arteris invented the industry's first commercial network on chip (NoC) SoC interconnect IP solutions and is the industry leader. Unlike traditional solutions, Arteris interconnect plug-and-play technology is flexible and efficient, allowing designers to optimize for throughput, power, latency and floorplan.

www.arteris.com
  • Arteris On-Chip Interconnect Technology: The Arteris Network-on-Chip (NoC) architecture borrows concepts from the computer networking arena and adapts them to system-on-chip design constraints. The network on chip solution optimizes performance, silicon area, and power, and reflects an in-depth understanding and integration of the constraints imposed by SoC implementations and semiconductor processes. By removing the inherent architectural limitations of traditional interconnect solutions, Arteris Network-on-Chip semiconductor IP offers a quantum leap in design quality and productivity, allowing SoC designers to achieve their ultimate design goals faster, easier and with less cost.
  • NcoreTM Cache Coherent Interconnect IP: Implements the same philosophy as the FlexNoC IP: Maximum configurability and scalability for the ultimate in product differentiation.
  • FlexNoC PhysicalTM: Builds upon the already layout-friendly FlexNoC IP to shorten the time required for timing closure, physical synthesis and place and route (SP&R).
  • FlexNoC Resilience Package: Complements FlexNoC fabric IP and implements hardware reliability & functional safety features required for automotive ISO 26262 or IEC 61508 compliance, and enhanced enterprise SSD endurance.
  • FlexWay: FlexWay is for design teams who use ARM AMBA AXI or multilayer AHB but are looking for a scalable solution to ultra-low power consumption and the automation of interconnect generation. It is particularly well suited to low-cost, low-power Internet-of-Things (IoT) edge devices.

Breker's Trek products and apps automatically generate multi-threaded test cases that verify your chip more quickly and more thoroughly. These test cases are portable from simulation to silicon, and from IP to full-chip level. Your verification engineers, embedded programmers, and bring-up team no longer have to hand-write throw-away tests, freeing them for revenue-generating tasks.

www.brekersystems.com
  • Trek: An advanced graph-based constraint solver that develops functional verification tests for complex digital designs. Trek generates tests directly from a visual graph-based specification of verification requirements, making the entire process easy and systematic.
  • TrekUVM: Automatically generates self-verifying test cases that run in existing transactional testbenches, including those compliant with the Universal Verification Methodology (UVM) standard. This verifies your chips more quickly and more thoroughly than using UVM alone to generate transactions. TrekUVM’s generated test cases target all aspects of full-chip verification and work in a variety of different environments.
  • TrekSoC: It links UVM testbenches to generated C test cases running in simulation on heterogeneous embedded processors within your system-on-chip (SoC). TrekSoC automatically generates self-verifying C test cases to run on the embedded processors in SoCs.
  • TrekSoC-Si: From the same inputs, TrekSoC-Si generates test cases that run on in-circuit emulation (ICE), FPGA prototypes, and actual silicon in your lab. TrekSoC-Si automatically generates self-verifying C test cases to run on the embedded processors in SoCs in in-circuit emulation (ICE), FPGA prototyping, and production silicon. TrekSoC-Si is a companion to TrekSoC, which generates test cases for simulation and acceleration.
  • The Cache Coherency TrekApp: Provides an automated solution for one of the toughest challenges in system verification: ensuring that multi-processor designs with multi-level caches structures remain consistent even under high system stress.

Magwel offers 3D field solver and simulation based analysis and design solutions for analog/mixed-signal, power management, automotive, and RF semiconductors. Magwel software products address power device design, ESD protection network simulation/analysis, latch-up analysis and power distribution network integrity. Leading semiconductor vendors use Magwel’s tools to improve productivity, avoid redesign, respins and field failures. Magwel is privately held and is headquartered in Leuven, Belgium.

www.magwel.com
  • ESDi: ESD Protection Network Analysis
  • RNi: Full Chip Resistance Analysis for Power and Ground Nets
  • PTM: Power Transistor Modeling
  • PTM-TR: Power Transistor Modeling: Transient
  • PTM-ET: Power Transistor Modeling: Electrothermal
  • PTM-GD: Power Transistor Modeling: Gate Delay
  • DevEM: Device Electromagnetic Modeler