AMIQ is a company which has pioneered the integrated development environments (IDEs) in hardware design and verification. They have focused on providing software tools that help engineers increase the speed and quality of code development, simplify maintenance, improve testbench reliability, and implement best coding practices.

www.amiq.com
  • DVT Eclipse IDE: Design and Verification Tools (DVT) is the first integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL.
  • Verissimo SystemVerilog Testbench Linter: Verissimo is a static code analysis tool that allows engineers accurately identify SystemVerilog improper language, semantics, and styling usage, as well as verification methodology violations.
  • Specador Documentation Generator: Specador is a tool that automatically generates accurate HTML documentation from source code comments.

Arteris provides Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) to System on Chip (SoC) makers so they can reduce cycle time, increase margins, and easily add functionality. Arteris invented the industry's first commercial network on chip (NoC) SoC interconnect IP solutions and is the industry leader. Unlike traditional solutions, Arteris interconnect plug-and-play technology is flexible and efficient, allowing designers to optimize for throughput, power, latency and floorplan.

www.arteris.com
  • FlexNoC5 NoC IP: FlexNoC 5 is Arteris' latest network-on-chip (NoC) interconnect IP, designed to revolutionize system-on-chip (SoC) design through its advanced physical awareness capabilities. It significantly enhances SoC layout quality and productivity by optimizing interconnects, reducing development time, improving performance, lowering power consumption, and minimizing die size. FlexNoC 5 supports a variety of topologies and is trusted by industry leaders for its performance and resilience in mobile, automotive, consumer, and enterprise applications. The IP supports essential industry-standard protocols and features built-in physical awareness, facilitating efficient routing and timing closure. Additionally, its Functional Safety (FuSa) option meets up to ASIL D requirements, making it suitable for safety-critical applications.
  • CodaCache Last-Level Cache IP: Critical challenges in developing SoC designs include performance optimization, data access, and power efficiency. CodaCache® addresses these design challenges effectively through performance-optimized caching, efficient data access, and power optimization techniques.
    CodaCache also tackles key challenges like system scalability, SoC integration, timing closure, layout congestion, and real-time processing by providing scalable cache solutions, seamless integration capabilities, and support for real-time processing.
    Using FlexNoC/FlexWay and CodaCache IPs in the same SoC provides a unique value by delivering a high-performance, power-efficient, and scalable solution that meets the demanding requirements of modern SoC designs while reducing development time, risk, and cost.
  • Magillem Registers Magillem® Registers offers a single source of truth methodology based on the IP-XACT standard, which not only targets the traditional need to manage registers, but also addresses today’s HW/SW integration challenges for large-scale SoCs.
    Magillem Registers enables quick and scalable automated implementation, cutting the time to market for the Hardware/Software Interface (HSI) generation in half.
    Key Features:
    Single Database: Import and capture memory map information into a single database (IP-XACT)
    Parameterization: including configurable properties, custom specific access types and register modes
    Comprehensive Checkers: Catch errors early in the process with built-in and custom checkers
    Standard Formats Support: Output standard formats for HW design and verification, embedded SW, and documentation
    Custom Templates: Advanced generation capability with support for custom template-based generators
    Merge/Flatten IP Memory: Enable easy update/manipulation/creation of new global memory map for a sub-system or SoC
    Tool Integration: Tight link with the connectivity tool to generate a system address map when both tools are combined
  • CSR Compiler: Streamline Hardware/Software Interface Foundation Creation with CSRCompiler and CSRSpec Complex software algorithms must control a growing array of specialized processors and hardware accelerators to deliver a robust product. The hardware/software interface (HSI) technology enables the software to control this hardware, which forms the basis of the entire design project. The CSRCompiler™ system, in combination with the CSRSpecTM language, automates the creation of this foundation.
    Build HSIs the Right Way With a Winning Methodology:
    CSRCompiler system and CSRSpec language form a complete register design solution for hardware, software, verification, and documentation. This comprehensive solution allows teams to manage their designs collaboratively from a single source specification, ensuring the entire team has a complete, correct, up-to-date register design ecosystem.
    CSRCompiler Key Features:
    Various input formats: CSRSpec language, SystemRDL, IP-XACT, spreadsheets ...
    Single source for generating RTL, digital verification, firmware, and documentation
    Extensive error/syntax checking with over 1,000 error checks
    Time-saving templates support
    Industry-standard buses
    Registers broadcast/alias and virtual registers support
    Wide memories and atomic access support
    Back door path mapping
    Coverage bins
    Parity checks